Layer arrangement and a wafer level package comprising the layer arrangement
The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging...
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| creator | NAGARAJAN RANGANATHAN HO BENG YEUNG XIE LING CHIDAMBARAM VIVEK CHEN BANGTAO |
| description | The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging). |
| format | Patent |
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The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).</description><language>eng</language><subject>ALLOYS ; BASIC ELECTRIC ELEMENTS ; CHEMISTRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FERROUS OR NON-FERROUS ALLOYS ; METALLURGY ; MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES ; MICROSTRUCTURAL TECHNOLOGY ; PERFORMING OPERATIONS ; PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS ; SEMICONDUCTOR DEVICES ; TRANSPORTING ; TREATMENT OF ALLOYS OR NON-FERROUS METALS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160119&DB=EPODOC&CC=US&NR=9240362B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160119&DB=EPODOC&CC=US&NR=9240362B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAGARAJAN RANGANATHAN</creatorcontrib><creatorcontrib>HO BENG YEUNG</creatorcontrib><creatorcontrib>XIE LING</creatorcontrib><creatorcontrib>CHIDAMBARAM VIVEK</creatorcontrib><creatorcontrib>CHEN BANGTAO</creatorcontrib><title>Layer arrangement and a wafer level package comprising the layer arrangement</title><description>The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. 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| subjects | ALLOYS BASIC ELECTRIC ELEMENTS CHEMISTRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FERROUS OR NON-FERROUS ALLOYS METALLURGY MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TRANSPORTING TREATMENT OF ALLOYS OR NON-FERROUS METALS |
| title | Layer arrangement and a wafer level package comprising the layer arrangement |
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