Read assist for an SRAM using a word line suppression circuit

A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression circuit. The word line suppression circuit includes two PFETs with their drains connected to the word line and their sources connected to the arr...

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Bibliographische Detailangaben

Hauptverfasser:	CLINTON MICHAEL PATRICK, MENEZES VINOD J, HOLLA LAKSHMIKANTHA V, HOUSTON THEODORE W
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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