Distributed phase detection for clock synchronization in multi-layer 3D stacks

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.