Cache management based on physical memory device characteristics

A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SAINATH VENKATESH, CHANDRAKAR RAHUL, SRINIVASAN VAIDYANATHAN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SAINATH VENKATESH
CHANDRAKAR RAHUL
SRINIVASAN VAIDYANATHAN
description A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9229862B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9229862B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9229862B23</originalsourceid><addsrcrecordid>eNqNyj0KwkAQBtBtLES9w1zAZoWQdGJQ7DV1mEw-3YXsDzuLkNvbeACr17ytOfcsDhQ48hsBsdLEiplSpOxW9cILBYRUVprx8QISx4WlonitXnRvNi9eFIefO0O367O_H5HTCM0siKjj8Ois7drGXuzpj_IFdowxVA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cache management based on physical memory device characteristics</title><source>esp@cenet</source><creator>SAINATH VENKATESH ; CHANDRAKAR RAHUL ; SRINIVASAN VAIDYANATHAN</creator><creatorcontrib>SAINATH VENKATESH ; CHANDRAKAR RAHUL ; SRINIVASAN VAIDYANATHAN</creatorcontrib><description>A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160105&amp;DB=EPODOC&amp;CC=US&amp;NR=9229862B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160105&amp;DB=EPODOC&amp;CC=US&amp;NR=9229862B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SAINATH VENKATESH</creatorcontrib><creatorcontrib>CHANDRAKAR RAHUL</creatorcontrib><creatorcontrib>SRINIVASAN VAIDYANATHAN</creatorcontrib><title>Cache management based on physical memory device characteristics</title><description>A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0KwkAQBtBtLES9w1zAZoWQdGJQ7DV1mEw-3YXsDzuLkNvbeACr17ytOfcsDhQ48hsBsdLEiplSpOxW9cILBYRUVprx8QISx4WlonitXnRvNi9eFIefO0O367O_H5HTCM0siKjj8Ois7drGXuzpj_IFdowxVA</recordid><startdate>20160105</startdate><enddate>20160105</enddate><creator>SAINATH VENKATESH</creator><creator>CHANDRAKAR RAHUL</creator><creator>SRINIVASAN VAIDYANATHAN</creator><scope>EVB</scope></search><sort><creationdate>20160105</creationdate><title>Cache management based on physical memory device characteristics</title><author>SAINATH VENKATESH ; CHANDRAKAR RAHUL ; SRINIVASAN VAIDYANATHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9229862B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SAINATH VENKATESH</creatorcontrib><creatorcontrib>CHANDRAKAR RAHUL</creatorcontrib><creatorcontrib>SRINIVASAN VAIDYANATHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SAINATH VENKATESH</au><au>CHANDRAKAR RAHUL</au><au>SRINIVASAN VAIDYANATHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cache management based on physical memory device characteristics</title><date>2016-01-05</date><risdate>2016</risdate><abstract>A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9229862B2
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Cache management based on physical memory device characteristics
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T21%3A49%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SAINATH%20VENKATESH&rft.date=2016-01-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9229862B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true