Receiver architecture for memory reads
A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory...
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creator | PAN LI VASUDEVAN NARASIMHAN FERTSCH MICHAEL THOMAS CHEN NAN |
description | A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9213487B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9213487B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9213487B23</originalsourceid><addsrcrecordid>eNrjZFALSk1OzSxLLVJILErOyCxJTS4pLUpVSMsvUshNzc0vqlQoSk1MKeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZZGhsYmFuZORsZEKAEAPN8nig</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Receiver architecture for memory reads</title><source>esp@cenet</source><creator>PAN LI ; VASUDEVAN NARASIMHAN ; FERTSCH MICHAEL THOMAS ; CHEN NAN</creator><creatorcontrib>PAN LI ; VASUDEVAN NARASIMHAN ; FERTSCH MICHAEL THOMAS ; CHEN NAN</creatorcontrib><description>A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20151215&DB=EPODOC&CC=US&NR=9213487B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20151215&DB=EPODOC&CC=US&NR=9213487B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PAN LI</creatorcontrib><creatorcontrib>VASUDEVAN NARASIMHAN</creatorcontrib><creatorcontrib>FERTSCH MICHAEL THOMAS</creatorcontrib><creatorcontrib>CHEN NAN</creatorcontrib><title>Receiver architecture for memory reads</title><description>A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFALSk1OzSxLLVJILErOyCxJTS4pLUpVSMsvUshNzc0vqlQoSk1MKeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZZGhsYmFuZORsZEKAEAPN8nig</recordid><startdate>20151215</startdate><enddate>20151215</enddate><creator>PAN LI</creator><creator>VASUDEVAN NARASIMHAN</creator><creator>FERTSCH MICHAEL THOMAS</creator><creator>CHEN NAN</creator><scope>EVB</scope></search><sort><creationdate>20151215</creationdate><title>Receiver architecture for memory reads</title><author>PAN LI ; VASUDEVAN NARASIMHAN ; FERTSCH MICHAEL THOMAS ; CHEN NAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9213487B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>PAN LI</creatorcontrib><creatorcontrib>VASUDEVAN NARASIMHAN</creatorcontrib><creatorcontrib>FERTSCH MICHAEL THOMAS</creatorcontrib><creatorcontrib>CHEN NAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PAN LI</au><au>VASUDEVAN NARASIMHAN</au><au>FERTSCH MICHAEL THOMAS</au><au>CHEN NAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Receiver architecture for memory reads</title><date>2015-12-15</date><risdate>2015</risdate><abstract>A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
title | Receiver architecture for memory reads |
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