High uniformity screen and epitaxial layers for CMOS devices
A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drai...
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| creator | KIM SUNG HWAN WANG LINGQUAN ZHAO DALONG LIU YUJIE PRADHAN SAMEER THOMPSON SCOTT E DUANE MICHAEL SHIFREN LUCIAN RANADE PUSHKAR BAKHISHEV TEYMUR HOFFMANN THOMAS |
| description | A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control. |
| format | Patent |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | High uniformity screen and epitaxial layers for CMOS devices |
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