Low-impedance power delivery for a packaged die

Low-impedance power delivery for a packaged die

A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane...

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Hauptverfasser: SCHIECK BRIAN S, TEMPLETON DONALD E, SHINH GURPREET, WAIZMAN ALEX
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator SCHIECK BRIAN S
TEMPLETON DONALD E
SHINH GURPREET
WAIZMAN ALEX
description A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9190396B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9190396B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9190396B23</originalsourceid><addsrcrecordid>eNrjZND3yS_XzcwtSE1JzEtOVSjIL08tUkhJzcksSy2qVEjLL1JIVChITM5OTE9NUUjJTOVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFQKWpeakl8aHBloaWBsaWZk5GxkQoAQC3ICpS</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Low-impedance power delivery for a packaged die</title><source>esp@cenet</source><creator>SCHIECK BRIAN S ; TEMPLETON DONALD E ; SHINH GURPREET ; WAIZMAN ALEX</creator><creatorcontrib>SCHIECK BRIAN S ; TEMPLETON DONALD E ; SHINH GURPREET ; WAIZMAN ALEX</creatorcontrib><description>A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151117&amp;DB=EPODOC&amp;CC=US&amp;NR=9190396B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151117&amp;DB=EPODOC&amp;CC=US&amp;NR=9190396B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SCHIECK BRIAN S</creatorcontrib><creatorcontrib>TEMPLETON DONALD E</creatorcontrib><creatorcontrib>SHINH GURPREET</creatorcontrib><creatorcontrib>WAIZMAN ALEX</creatorcontrib><title>Low-impedance power delivery for a packaged die</title><description>A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3yS_XzcwtSE1JzEtOVSjIL08tUkhJzcksSy2qVEjLL1JIVChITM5OTE9NUUjJTOVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFQKWpeakl8aHBloaWBsaWZk5GxkQoAQC3ICpS</recordid><startdate>20151117</startdate><enddate>20151117</enddate><creator>SCHIECK BRIAN S</creator><creator>TEMPLETON DONALD E</creator><creator>SHINH GURPREET</creator><creator>WAIZMAN ALEX</creator><scope>EVB</scope></search><sort><creationdate>20151117</creationdate><title>Low-impedance power delivery for a packaged die</title><author>SCHIECK BRIAN S ; TEMPLETON DONALD E ; SHINH GURPREET ; WAIZMAN ALEX</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9190396B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SCHIECK BRIAN S</creatorcontrib><creatorcontrib>TEMPLETON DONALD E</creatorcontrib><creatorcontrib>SHINH GURPREET</creatorcontrib><creatorcontrib>WAIZMAN ALEX</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SCHIECK BRIAN S</au><au>TEMPLETON DONALD E</au><au>SHINH GURPREET</au><au>WAIZMAN ALEX</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Low-impedance power delivery for a packaged die</title><date>2015-11-17</date><risdate>2015</risdate><abstract>A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Low-impedance power delivery for a packaged die
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T22%3A28%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SCHIECK%20BRIAN%20S&rft.date=2015-11-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9190396B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true