Data and phase locking buffer design in a two-way handshake system

A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguou...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PRAKASAM RAMKUMAR, YANG GENKUN JASON
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator PRAKASAM RAMKUMAR
YANG GENKUN JASON
description A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9182993B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9182993B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9182993B23</originalsourceid><addsrcrecordid>eNqNyjESgjAQBdA0Fo56h38BCqExLaJjr9bMChuSATcZNw7D7bXwAFaveWtTN5QJJD2SJ2VMsRuDDHi8neMXetYwCIKAkOdYzLTAf7d6Ghm6aObn1qwcTcq7nxuD8-l2vBScYsuaqGPh3N6vdn8ora3qsvqjfACHpDFC</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data and phase locking buffer design in a two-way handshake system</title><source>esp@cenet</source><creator>PRAKASAM RAMKUMAR ; YANG GENKUN JASON</creator><creatorcontrib>PRAKASAM RAMKUMAR ; YANG GENKUN JASON</creatorcontrib><description>A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151110&amp;DB=EPODOC&amp;CC=US&amp;NR=9182993B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151110&amp;DB=EPODOC&amp;CC=US&amp;NR=9182993B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PRAKASAM RAMKUMAR</creatorcontrib><creatorcontrib>YANG GENKUN JASON</creatorcontrib><title>Data and phase locking buffer design in a two-way handshake system</title><description>A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjESgjAQBdA0Fo56h38BCqExLaJjr9bMChuSATcZNw7D7bXwAFaveWtTN5QJJD2SJ2VMsRuDDHi8neMXetYwCIKAkOdYzLTAf7d6Ghm6aObn1qwcTcq7nxuD8-l2vBScYsuaqGPh3N6vdn8ora3qsvqjfACHpDFC</recordid><startdate>20151110</startdate><enddate>20151110</enddate><creator>PRAKASAM RAMKUMAR</creator><creator>YANG GENKUN JASON</creator><scope>EVB</scope></search><sort><creationdate>20151110</creationdate><title>Data and phase locking buffer design in a two-way handshake system</title><author>PRAKASAM RAMKUMAR ; YANG GENKUN JASON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9182993B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>PRAKASAM RAMKUMAR</creatorcontrib><creatorcontrib>YANG GENKUN JASON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PRAKASAM RAMKUMAR</au><au>YANG GENKUN JASON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data and phase locking buffer design in a two-way handshake system</title><date>2015-11-10</date><risdate>2015</risdate><abstract>A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9182993B2
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
title Data and phase locking buffer design in a two-way handshake system
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-06T01%3A11%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PRAKASAM%20RAMKUMAR&rft.date=2015-11-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9182993B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true