Method and system for forward error correction of interleaved-formated data

In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate....

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Hauptverfasser:	RAO RAGHAVENDAR M, MAZAHREH RAIED N
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY
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creator	RAO RAGHAVENDAR M MAZAHREH RAIED N
description	In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9112529B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9112529B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9112529B13</originalsourceid><addsrcrecordid>eNqNijEKwkAQRbexEPUOc4EUG7FIq0QEsVLrMOz-xUCyE2YHxdsbwQNYPB4P3tKdL7CHROIcqbyLYaQk-uXFGgmqcwVRRbBeMkmiPht0AD8Rq_kb2RApsvHaLRIPBZufV46O7e1wqjBJhzJxQIZ192vjfb2rm73f_rF8ABRKNXQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and system for forward error correction of interleaved-formated data</title><source>esp@cenet</source><creator>RAO RAGHAVENDAR M ; MAZAHREH RAIED N</creator><creatorcontrib>RAO RAGHAVENDAR M ; MAZAHREH RAIED N</creatorcontrib><description>In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; DECODING ; ELECTRICITY</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150818&DB=EPODOC&CC=US&NR=9112529B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150818&DB=EPODOC&CC=US&NR=9112529B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAO RAGHAVENDAR M</creatorcontrib><creatorcontrib>MAZAHREH RAIED N</creatorcontrib><title>Method and system for forward error correction of interleaved-formated data</title><description>In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNijEKwkAQRbexEPUOc4EUG7FIq0QEsVLrMOz-xUCyE2YHxdsbwQNYPB4P3tKdL7CHROIcqbyLYaQk-uXFGgmqcwVRRbBeMkmiPht0AD8Rq_kb2RApsvHaLRIPBZufV46O7e1wqjBJhzJxQIZ192vjfb2rm73f_rF8ABRKNXQ</recordid><startdate>20150818</startdate><enddate>20150818</enddate><creator>RAO RAGHAVENDAR M</creator><creator>MAZAHREH RAIED N</creator><scope>EVB</scope></search><sort><creationdate>20150818</creationdate><title>Method and system for forward error correction of interleaved-formated data</title><author>RAO RAGHAVENDAR M ; MAZAHREH RAIED N</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9112529B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>RAO RAGHAVENDAR M</creatorcontrib><creatorcontrib>MAZAHREH RAIED N</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAO RAGHAVENDAR M</au><au>MAZAHREH RAIED N</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and system for forward error correction of interleaved-formated data</title><date>2015-08-18</date><risdate>2015</risdate><abstract>In one embodiment, a device is provided. The device includes a first formatting circuit configured to add zero padding bits to a received data block. An FEC encoder circuit is coupled to the first formatting circuit and is configured to determine parity bits for the data block at a first code rate. A second formatting circuit is coupled to the FEC encoder circuit and is configured to combine the parity bits with the data block and remove the zero padding bits to provide an FEC coded data block at a second code rate. The second code rate is less than the first code rate.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY
title	Method and system for forward error correction of interleaved-formated data
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T06%3A09%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RAO%20RAGHAVENDAR%20M&rft.date=2015-08-18&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9112529B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true