Digital signal processing block
An apparatus is disclosed. This apparatus includes a digital signal processing ("DSP") block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier op...
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| creator | SIMKINS JAMES M WALKE RICHARD L THENDEAN JOHN M ELKINS ADAM WENNEKAMP WAYNE E |
| description | An apparatus is disclosed. This apparatus includes a digital signal processing ("DSP") block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ("ALU") block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9081634B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9081634B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9081634B13</originalsourceid><addsrcrecordid>eNrjZJB3yUzPLEnMUSjOTM8DUgVF-cmpxcWZeekKSTn5ydk8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-NNjSwMLQzNjEydCYCCUA6QUkuA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Digital signal processing block</title><source>esp@cenet</source><creator>SIMKINS JAMES M ; WALKE RICHARD L ; THENDEAN JOHN M ; ELKINS ADAM ; WENNEKAMP WAYNE E</creator><creatorcontrib>SIMKINS JAMES M ; WALKE RICHARD L ; THENDEAN JOHN M ; ELKINS ADAM ; WENNEKAMP WAYNE E</creatorcontrib><description>An apparatus is disclosed. This apparatus includes a digital signal processing ("DSP") block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ("ALU") block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150714&DB=EPODOC&CC=US&NR=9081634B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150714&DB=EPODOC&CC=US&NR=9081634B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SIMKINS JAMES M</creatorcontrib><creatorcontrib>WALKE RICHARD L</creatorcontrib><creatorcontrib>THENDEAN JOHN M</creatorcontrib><creatorcontrib>ELKINS ADAM</creatorcontrib><creatorcontrib>WENNEKAMP WAYNE E</creatorcontrib><title>Digital signal processing block</title><description>An apparatus is disclosed. This apparatus includes a digital signal processing ("DSP") block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ("ALU") block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB3yUzPLEnMUSjOTM8DUgVF-cmpxcWZeekKSTn5ydk8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-NNjSwMLQzNjEydCYCCUA6QUkuA</recordid><startdate>20150714</startdate><enddate>20150714</enddate><creator>SIMKINS JAMES M</creator><creator>WALKE RICHARD L</creator><creator>THENDEAN JOHN M</creator><creator>ELKINS ADAM</creator><creator>WENNEKAMP WAYNE E</creator><scope>EVB</scope></search><sort><creationdate>20150714</creationdate><title>Digital signal processing block</title><author>SIMKINS JAMES M ; WALKE RICHARD L ; THENDEAN JOHN M ; ELKINS ADAM ; WENNEKAMP WAYNE E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9081634B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SIMKINS JAMES M</creatorcontrib><creatorcontrib>WALKE RICHARD L</creatorcontrib><creatorcontrib>THENDEAN JOHN M</creatorcontrib><creatorcontrib>ELKINS ADAM</creatorcontrib><creatorcontrib>WENNEKAMP WAYNE E</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SIMKINS JAMES M</au><au>WALKE RICHARD L</au><au>THENDEAN JOHN M</au><au>ELKINS ADAM</au><au>WENNEKAMP WAYNE E</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Digital signal processing block</title><date>2015-07-14</date><risdate>2015</risdate><abstract>An apparatus is disclosed. This apparatus includes a digital signal processing ("DSP") block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit ("ALU") block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Digital signal processing block |
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