Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach

Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layer...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KARLSSON OLOV, HONG ZHENDONG, BODKE ASHISH
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KARLSSON OLOV
HONG ZHENDONG
BODKE ASHISH
description Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9059156B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9059156B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9059156B23</originalsourceid><addsrcrecordid>eNqNjLsKwkAQRdNYiPoP9wcEH0RIqxhsrNQ6jJtJMrjZWbJrIH_vCn6A1S3uOWeeTVeOndbQBo0OvbgW5MDDU949glgxUjN6jmTRUmSESOaFUlx5vqPmUQxjFALBd1MQk7iRvA7p8xokijo4cmopxb8B8n5QMt0ymzVkA69-u8iQkqfLOnkVB0-GHcfqcSs2ebHND8fd_g_kAw6xRfg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach</title><source>esp@cenet</source><creator>KARLSSON OLOV ; HONG ZHENDONG ; BODKE ASHISH</creator><creatorcontrib>KARLSSON OLOV ; HONG ZHENDONG ; BODKE ASHISH</creatorcontrib><description>Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150616&amp;DB=EPODOC&amp;CC=US&amp;NR=9059156B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150616&amp;DB=EPODOC&amp;CC=US&amp;NR=9059156B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KARLSSON OLOV</creatorcontrib><creatorcontrib>HONG ZHENDONG</creatorcontrib><creatorcontrib>BODKE ASHISH</creatorcontrib><title>Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach</title><description>Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsKwkAQRdNYiPoP9wcEH0RIqxhsrNQ6jJtJMrjZWbJrIH_vCn6A1S3uOWeeTVeOndbQBo0OvbgW5MDDU949glgxUjN6jmTRUmSESOaFUlx5vqPmUQxjFALBd1MQk7iRvA7p8xokijo4cmopxb8B8n5QMt0ymzVkA69-u8iQkqfLOnkVB0-GHcfqcSs2ebHND8fd_g_kAw6xRfg</recordid><startdate>20150616</startdate><enddate>20150616</enddate><creator>KARLSSON OLOV</creator><creator>HONG ZHENDONG</creator><creator>BODKE ASHISH</creator><scope>EVB</scope></search><sort><creationdate>20150616</creationdate><title>Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach</title><author>KARLSSON OLOV ; HONG ZHENDONG ; BODKE ASHISH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9059156B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KARLSSON OLOV</creatorcontrib><creatorcontrib>HONG ZHENDONG</creatorcontrib><creatorcontrib>BODKE ASHISH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KARLSSON OLOV</au><au>HONG ZHENDONG</au><au>BODKE ASHISH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach</title><date>2015-06-16</date><risdate>2015</risdate><abstract>Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9059156B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T15%3A32%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KARLSSON%20OLOV&rft.date=2015-06-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9059156B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true