Timing signal adjustment for data storage

An integrated circuit includes a delay circuit, a buffer circuit, and a storage circuit. The delay circuit delays a first timing signal to generate a second timing signal. The buffer circuit generates a third timing signal for transmission to an external device. The third timing signal is generated...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	OOI BENG LEE, PHOON HEE KONG, NG BEE YEE
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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