Semiconductor device processing with reduced wiring puddle formation

Semiconductor device processing with reduced wiring puddle formation

A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer;...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KO TZE-MAN, XU YIHENG, DYER THOMAS W, HENRY HANAKO, YAO SHAONING
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KO TZE-MAN
XU YIHENG
DYER THOMAS W
HENRY HANAKO
YAO SHAONING
description A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9018097B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9018097B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9018097B23</originalsourceid><addsrcrecordid>eNrjZHAJTs3NTM7PSylNLskvUkhJLctMTlUoKMpPTi0uzsxLVyjPLMlQKEoFyqemADlFILGC0pSUnFSFtPyi3MSSzPw8HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsaWBoYWBp7mRkTIQSALc5M2I</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device processing with reduced wiring puddle formation</title><source>esp@cenet</source><creator>KO TZE-MAN ; XU YIHENG ; DYER THOMAS W ; HENRY HANAKO ; YAO SHAONING</creator><creatorcontrib>KO TZE-MAN ; XU YIHENG ; DYER THOMAS W ; HENRY HANAKO ; YAO SHAONING</creatorcontrib><description>A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150428&amp;DB=EPODOC&amp;CC=US&amp;NR=9018097B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150428&amp;DB=EPODOC&amp;CC=US&amp;NR=9018097B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KO TZE-MAN</creatorcontrib><creatorcontrib>XU YIHENG</creatorcontrib><creatorcontrib>DYER THOMAS W</creatorcontrib><creatorcontrib>HENRY HANAKO</creatorcontrib><creatorcontrib>YAO SHAONING</creatorcontrib><title>Semiconductor device processing with reduced wiring puddle formation</title><description>A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAJTs3NTM7PSylNLskvUkhJLctMTlUoKMpPTi0uzsxLVyjPLMlQKEoFyqemADlFILGC0pSUnFSFtPyi3MSSzPw8HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsaWBoYWBp7mRkTIQSALc5M2I</recordid><startdate>20150428</startdate><enddate>20150428</enddate><creator>KO TZE-MAN</creator><creator>XU YIHENG</creator><creator>DYER THOMAS W</creator><creator>HENRY HANAKO</creator><creator>YAO SHAONING</creator><scope>EVB</scope></search><sort><creationdate>20150428</creationdate><title>Semiconductor device processing with reduced wiring puddle formation</title><author>KO TZE-MAN ; XU YIHENG ; DYER THOMAS W ; HENRY HANAKO ; YAO SHAONING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9018097B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KO TZE-MAN</creatorcontrib><creatorcontrib>XU YIHENG</creatorcontrib><creatorcontrib>DYER THOMAS W</creatorcontrib><creatorcontrib>HENRY HANAKO</creatorcontrib><creatorcontrib>YAO SHAONING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KO TZE-MAN</au><au>XU YIHENG</au><au>DYER THOMAS W</au><au>HENRY HANAKO</au><au>YAO SHAONING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device processing with reduced wiring puddle formation</title><date>2015-04-28</date><risdate>2015</risdate><abstract>A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9018097B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor device processing with reduced wiring puddle formation
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T05%3A14%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KO%20TZE-MAN&rft.date=2015-04-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9018097B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true