Avoiding BIST and MBIST intrusion logic in critical timing paths

Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	VENKATARAMANAN GANESH, AREKAPUDI SRIKANTH, EATON CRAIG D
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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