Forward error correction

In one embodiment, a circuit for FEC decoding includes first and second syndrome calculation circuits, configured to calculate FEC syndromes for rows and columns of symbols in a de-interleaved format, respectively. A decoding circuit is configured to arrange the symbols into windows. Each window inc...

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Bibliographische Detailangaben
Hauptverfasser: PFISTER HENRY D, RAO RAGHAVENDAR M, NARAYANAN KRISHNA R, MAZAHREH RAIED N
Format: Patent
Sprache:eng
Schlagworte:
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