Non-blocking processor bus bridge for network processors or the like

Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with...

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Bibliographische Detailangaben

Hauptverfasser:	BYRNE RICHARD J, MASTERS DAVID S
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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