Latency sensitive software interrupt and thread scheduling

Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WATERS BRADLEY M, ZHU DANYU
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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