Method for forming through silicon via with wafer backside protection
Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surfac...
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| creator | SEE ALEX KAI HUNG CONG HAI TAN YUN LING LEONG LUP SAN RAO XUESONG ZOU ZHENG LIU HUANG |
| description | Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8940637B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8940637B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8940637B23</originalsourceid><addsrcrecordid>eNrjZHD1TS3JyE9RSMsvAuHczLx0hZKMovzS9AyF4syczOT8PIWyzESF8sySDIXyxLTUIoWkxOTs4syUVIWCovyS1OSSzPw8HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsYWliYGZs7mRkTIQSAKjnM0I</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for forming through silicon via with wafer backside protection</title><source>esp@cenet</source><creator>SEE ALEX KAI HUNG ; CONG HAI ; TAN YUN LING ; LEONG LUP SAN ; RAO XUESONG ; ZOU ZHENG ; LIU HUANG</creator><creatorcontrib>SEE ALEX KAI HUNG ; CONG HAI ; TAN YUN LING ; LEONG LUP SAN ; RAO XUESONG ; ZOU ZHENG ; LIU HUANG</creatorcontrib><description>Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150127&DB=EPODOC&CC=US&NR=8940637B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150127&DB=EPODOC&CC=US&NR=8940637B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SEE ALEX KAI HUNG</creatorcontrib><creatorcontrib>CONG HAI</creatorcontrib><creatorcontrib>TAN YUN LING</creatorcontrib><creatorcontrib>LEONG LUP SAN</creatorcontrib><creatorcontrib>RAO XUESONG</creatorcontrib><creatorcontrib>ZOU ZHENG</creatorcontrib><creatorcontrib>LIU HUANG</creatorcontrib><title>Method for forming through silicon via with wafer backside protection</title><description>Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD1TS3JyE9RSMsvAuHczLx0hZKMovzS9AyF4syczOT8PIWyzESF8sySDIXyxLTUIoWkxOTs4syUVIWCovyS1OSSzPw8HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsYWliYGZs7mRkTIQSAKjnM0I</recordid><startdate>20150127</startdate><enddate>20150127</enddate><creator>SEE ALEX KAI HUNG</creator><creator>CONG HAI</creator><creator>TAN YUN LING</creator><creator>LEONG LUP SAN</creator><creator>RAO XUESONG</creator><creator>ZOU ZHENG</creator><creator>LIU HUANG</creator><scope>EVB</scope></search><sort><creationdate>20150127</creationdate><title>Method for forming through silicon via with wafer backside protection</title><author>SEE ALEX KAI HUNG ; CONG HAI ; TAN YUN LING ; LEONG LUP SAN ; RAO XUESONG ; ZOU ZHENG ; LIU HUANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8940637B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SEE ALEX KAI HUNG</creatorcontrib><creatorcontrib>CONG HAI</creatorcontrib><creatorcontrib>TAN YUN LING</creatorcontrib><creatorcontrib>LEONG LUP SAN</creatorcontrib><creatorcontrib>RAO XUESONG</creatorcontrib><creatorcontrib>ZOU ZHENG</creatorcontrib><creatorcontrib>LIU HUANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SEE ALEX KAI HUNG</au><au>CONG HAI</au><au>TAN YUN LING</au><au>LEONG LUP SAN</au><au>RAO XUESONG</au><au>ZOU ZHENG</au><au>LIU HUANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming through silicon via with wafer backside protection</title><date>2015-01-27</date><risdate>2015</risdate><abstract>Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method for forming through silicon via with wafer backside protection |
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