Thermal via for 3D integrated circuits structures

Thermal via for 3D integrated circuits structures

A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is forme...

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Hauptverfasser: SULLIVAN TIMOTHY D, HAUSER MICHAEL J, DAUBENSPECK TIMOTHY H, MUZZY CHRISTOPHER D, GAMBINO JEFFREY P, SAUTER WOLFGANG
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator SULLIVAN TIMOTHY D
HAUSER MICHAEL J
DAUBENSPECK TIMOTHY H
MUZZY CHRISTOPHER D
GAMBINO JEFFREY P
SAUTER WOLFGANG
description A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Thermal via for 3D integrated circuits structures
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