Method of sharing and re-using timing models in a chip across multiple voltage domains

A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	FLUHR ERIC J, SINHA DEBJIT, VISWESWARIAH CHANDRAMOULI, ZOLOTOV VLADIMIR, SHUMA STEPHEN G, VENKATESWARAN NATESAN, WOOD MICHAEL H
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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