Low latency data transfer between clock domains operated in various synchronization modes

Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequ...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WEBEL TOBIAS, MAK PAK-KIN, FERRAIOLO FRANK D, HARRER HUBERT, TONG CHING-LUNG L, WEISS ULRICH, DREPS DANIEL M
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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