Patterning embedded control lines for vertically stacked semiconductor elements

The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	JUNG CHULMIN, SUBRAMANIAN PARAMASIYAN KAMATCHI, MANOS PETER NICHOLAS, AHN YONGCHUL, KHOURY MAROUN, SETIADI DADI, KIM YOUNGPIL, KIM JINYOUNG, LEE HYUNG-KYU, KHOUEIR ANTOINE, LIOU HSING-KUEN
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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