Repairable multi-layer memory chip stack and method thereof

A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus,...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LUO KUN-LUN, CHEN CHEN-AN, CHEN YEE-WEN, WU MING-HSUEH
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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