Scan compression architecture with bypassable scan chains for low test mode power
This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the se...
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creator | PAREKHJI RUBIN AJIT TIWARI RAJESH KUMAR RAVI SRIVATHS |
description | This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations. |
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Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.</description><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20141007&DB=EPODOC&CC=US&NR=8856601B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20141007&DB=EPODOC&CC=US&NR=8856601B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PAREKHJI RUBIN AJIT</creatorcontrib><creatorcontrib>TIWARI RAJESH KUMAR</creatorcontrib><creatorcontrib>RAVI SRIVATHS</creatorcontrib><title>Scan compression architecture with bypassable scan chains for low test mode power</title><description>This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0KAjEQBtA0FqLeYS4g-IPL1opiK6v1Mhu_JYFsJmQiwdsL4gGsXvPm5tZZjmRlShmqXiJxts4X2PLKoOqLo-GdWJWHANLvduyj0iiZglQq0EKTPEFJKvLSzEYOitXPhaHL-X66rpGkhya2iCj9o2vbQ9Nstsfd_o_yAaVDN9A</recordid><startdate>20141007</startdate><enddate>20141007</enddate><creator>PAREKHJI RUBIN AJIT</creator><creator>TIWARI RAJESH KUMAR</creator><creator>RAVI SRIVATHS</creator><scope>EVB</scope></search><sort><creationdate>20141007</creationdate><title>Scan compression architecture with bypassable scan chains for low test mode power</title><author>PAREKHJI RUBIN AJIT ; TIWARI RAJESH KUMAR ; RAVI SRIVATHS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8856601B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>PAREKHJI RUBIN AJIT</creatorcontrib><creatorcontrib>TIWARI RAJESH KUMAR</creatorcontrib><creatorcontrib>RAVI SRIVATHS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PAREKHJI RUBIN AJIT</au><au>TIWARI RAJESH KUMAR</au><au>RAVI SRIVATHS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Scan compression architecture with bypassable scan chains for low test mode power</title><date>2014-10-07</date><risdate>2014</risdate><abstract>This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.</abstract><oa>free_for_read</oa></addata></record> |
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title | Scan compression architecture with bypassable scan chains for low test mode power |
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