FinFET trench circuit

FinFET trench circuit

A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by util...

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Hauptverfasser: STANDAERT THEODORUS EDUARDUS, FALTERMEIER JONATHAN E, CHENG KANGGUO, BASKER VEERARAGHAVAN S
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator STANDAERT THEODORUS EDUARDUS
FALTERMEIER JONATHAN E
CHENG KANGGUO
BASKER VEERARAGHAVAN S
description A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8835250B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8835250B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8835250B23</originalsourceid><addsrcrecordid>eNrjZBB1y8xzcw1RKClKzUvOUEjOLEouzSzhYWBNS8wpTuWF0twMCkBFzh66qQX58anFBYnJqXmpJfGhwRYWxqZGpgZORsZEKAEADw4gfw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FinFET trench circuit</title><source>esp@cenet</source><creator>STANDAERT THEODORUS EDUARDUS ; FALTERMEIER JONATHAN E ; CHENG KANGGUO ; BASKER VEERARAGHAVAN S</creator><creatorcontrib>STANDAERT THEODORUS EDUARDUS ; FALTERMEIER JONATHAN E ; CHENG KANGGUO ; BASKER VEERARAGHAVAN S</creatorcontrib><description>A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140916&amp;DB=EPODOC&amp;CC=US&amp;NR=8835250B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140916&amp;DB=EPODOC&amp;CC=US&amp;NR=8835250B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>STANDAERT THEODORUS EDUARDUS</creatorcontrib><creatorcontrib>FALTERMEIER JONATHAN E</creatorcontrib><creatorcontrib>CHENG KANGGUO</creatorcontrib><creatorcontrib>BASKER VEERARAGHAVAN S</creatorcontrib><title>FinFET trench circuit</title><description>A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB1y8xzcw1RKClKzUvOUEjOLEouzSzhYWBNS8wpTuWF0twMCkBFzh66qQX58anFBYnJqXmpJfGhwRYWxqZGpgZORsZEKAEADw4gfw</recordid><startdate>20140916</startdate><enddate>20140916</enddate><creator>STANDAERT THEODORUS EDUARDUS</creator><creator>FALTERMEIER JONATHAN E</creator><creator>CHENG KANGGUO</creator><creator>BASKER VEERARAGHAVAN S</creator><scope>EVB</scope></search><sort><creationdate>20140916</creationdate><title>FinFET trench circuit</title><author>STANDAERT THEODORUS EDUARDUS ; FALTERMEIER JONATHAN E ; CHENG KANGGUO ; BASKER VEERARAGHAVAN S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8835250B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>STANDAERT THEODORUS EDUARDUS</creatorcontrib><creatorcontrib>FALTERMEIER JONATHAN E</creatorcontrib><creatorcontrib>CHENG KANGGUO</creatorcontrib><creatorcontrib>BASKER VEERARAGHAVAN S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>STANDAERT THEODORUS EDUARDUS</au><au>FALTERMEIER JONATHAN E</au><au>CHENG KANGGUO</au><au>BASKER VEERARAGHAVAN S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FinFET trench circuit</title><date>2014-09-16</date><risdate>2014</risdate><abstract>A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title FinFET trench circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T04%3A45%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=STANDAERT%20THEODORUS%20EDUARDUS&rft.date=2014-09-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8835250B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true