Automating current-aware integrated circuit and package design and optimization

Automating current-aware integrated circuit and package design and optimization

A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-ti...

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Hauptverfasser: SHIN JEONGHEE, DARRINGER JOHN
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator SHIN JEONGHEE
DARRINGER JOHN
description A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Automating current-aware integrated circuit and package design and optimization
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