Hierarchical verification of clock domain crossings

The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verificatio...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SABBAGH ROJER RAJI, VISWANATHAN PRIYA, KWOK KA-KEI, SATHIANATHAN RAMESH
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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