Dynamic and idle power reduction sequence using recombinant clock and power gating
Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other emb...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | SRINIVASAN SRIKANTH T TAN SIN S LOOI LILY PAO JOURDAN STEPHAN J RADHAKRISHNAN SIVAKUMAR |
| description | Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8782456B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8782456B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8782456B23</originalsourceid><addsrcrecordid>eNqNizsOwjAQBd1QIOAOewGa8EvNT9R86mjZPCILZ21iW4jbEwEHoJpiZobmuH0pt1aItSZbO1DwT3TUoc6SrFeKeGSogHK02vRCfHu1yppInJf75_xODac-GZvBjV3E5MeRof3uvDlMEXyFGFigSNXlVK7KYr5YrovZH8kbuD44Ag</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dynamic and idle power reduction sequence using recombinant clock and power gating</title><source>esp@cenet</source><creator>SRINIVASAN SRIKANTH T ; TAN SIN S ; LOOI LILY PAO ; JOURDAN STEPHAN J ; RADHAKRISHNAN SIVAKUMAR</creator><creatorcontrib>SRINIVASAN SRIKANTH T ; TAN SIN S ; LOOI LILY PAO ; JOURDAN STEPHAN J ; RADHAKRISHNAN SIVAKUMAR</creatorcontrib><description>Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140715&DB=EPODOC&CC=US&NR=8782456B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140715&DB=EPODOC&CC=US&NR=8782456B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SRINIVASAN SRIKANTH T</creatorcontrib><creatorcontrib>TAN SIN S</creatorcontrib><creatorcontrib>LOOI LILY PAO</creatorcontrib><creatorcontrib>JOURDAN STEPHAN J</creatorcontrib><creatorcontrib>RADHAKRISHNAN SIVAKUMAR</creatorcontrib><title>Dynamic and idle power reduction sequence using recombinant clock and power gating</title><description>Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizsOwjAQBd1QIOAOewGa8EvNT9R86mjZPCILZ21iW4jbEwEHoJpiZobmuH0pt1aItSZbO1DwT3TUoc6SrFeKeGSogHK02vRCfHu1yppInJf75_xODac-GZvBjV3E5MeRof3uvDlMEXyFGFigSNXlVK7KYr5YrovZH8kbuD44Ag</recordid><startdate>20140715</startdate><enddate>20140715</enddate><creator>SRINIVASAN SRIKANTH T</creator><creator>TAN SIN S</creator><creator>LOOI LILY PAO</creator><creator>JOURDAN STEPHAN J</creator><creator>RADHAKRISHNAN SIVAKUMAR</creator><scope>EVB</scope></search><sort><creationdate>20140715</creationdate><title>Dynamic and idle power reduction sequence using recombinant clock and power gating</title><author>SRINIVASAN SRIKANTH T ; TAN SIN S ; LOOI LILY PAO ; JOURDAN STEPHAN J ; RADHAKRISHNAN SIVAKUMAR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8782456B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SRINIVASAN SRIKANTH T</creatorcontrib><creatorcontrib>TAN SIN S</creatorcontrib><creatorcontrib>LOOI LILY PAO</creatorcontrib><creatorcontrib>JOURDAN STEPHAN J</creatorcontrib><creatorcontrib>RADHAKRISHNAN SIVAKUMAR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SRINIVASAN SRIKANTH T</au><au>TAN SIN S</au><au>LOOI LILY PAO</au><au>JOURDAN STEPHAN J</au><au>RADHAKRISHNAN SIVAKUMAR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dynamic and idle power reduction sequence using recombinant clock and power gating</title><date>2014-07-15</date><risdate>2014</risdate><abstract>Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US8782456B2 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Dynamic and idle power reduction sequence using recombinant clock and power gating |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T11%3A43%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SRINIVASAN%20SRIKANTH%20T&rft.date=2014-07-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8782456B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |