Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cell...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WANG LUANG-TERNG, HSU POING, WEN XIAQING, LIN MENGYI, WANG HSIN-PO, CHAO HAO-JAN, KAO SHIHIA
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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