Decoder providing separate clock and enable for scan path segments

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures,...

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Bibliographische Detailangaben

Hauptverfasser:	WHETSEL LEE D, SAXENA JAYASHREE
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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