Non-volatile memory and method having a memory array with a high-speed, short bit-line portion

A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first porti...

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Bibliographische Detailangaben

Hauptverfasser:	PARK JONGMIN, LEE SEUNGPIL
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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