Processor for performing multiply-add operations on packed data

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data element...

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Bibliographische Detailangaben
Hauptverfasser: KOWASHI EIICHI, MENNEMEIER LARRY M, MITTAL MILLIND, WITT WOLF C, PELEG ALEXANDER, EITAN BENNY, DULONG CAROLE
Format: Patent
Sprache:eng
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