Semiconductor packages and methods of packaging semiconductor devices
A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with cond...
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| creator | NG CATHERINE BEE LIANG DIMAANO ANTONIO JR B ENG KIAN TENG GAN RICHARD TE WANG CHUEN KHIANG SUTHIWONGSUNTHORN NATHAPONG SAE LE KRIANGSAK |
| description | A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8716873B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8716873B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8716873B23</originalsourceid><addsrcrecordid>eNrjZHANTs3NTM7PSylNLskvUihITM5OTE8tVkjMS1HITS3JyE8pVshPg4pn5qUrFKOoT0kty0xOLeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFQN2peakl8aHBFuaGZhbmxk5GxkQoAQDQpTOP</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor packages and methods of packaging semiconductor devices</title><source>esp@cenet</source><creator>NG CATHERINE BEE LIANG ; DIMAANO ANTONIO JR B ; ENG KIAN TENG ; GAN RICHARD TE ; WANG CHUEN KHIANG ; SUTHIWONGSUNTHORN NATHAPONG ; SAE LE KRIANGSAK</creator><creatorcontrib>NG CATHERINE BEE LIANG ; DIMAANO ANTONIO JR B ; ENG KIAN TENG ; GAN RICHARD TE ; WANG CHUEN KHIANG ; SUTHIWONGSUNTHORN NATHAPONG ; SAE LE KRIANGSAK</creatorcontrib><description>A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140506&DB=EPODOC&CC=US&NR=8716873B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140506&DB=EPODOC&CC=US&NR=8716873B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NG CATHERINE BEE LIANG</creatorcontrib><creatorcontrib>DIMAANO ANTONIO JR B</creatorcontrib><creatorcontrib>ENG KIAN TENG</creatorcontrib><creatorcontrib>GAN RICHARD TE</creatorcontrib><creatorcontrib>WANG CHUEN KHIANG</creatorcontrib><creatorcontrib>SUTHIWONGSUNTHORN NATHAPONG</creatorcontrib><creatorcontrib>SAE LE KRIANGSAK</creatorcontrib><title>Semiconductor packages and methods of packaging semiconductor devices</title><description>A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHANTs3NTM7PSylNLskvUihITM5OTE8tVkjMS1HITS3JyE8pVshPg4pn5qUrFKOoT0kty0xOLeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFQN2peakl8aHBFuaGZhbmxk5GxkQoAQDQpTOP</recordid><startdate>20140506</startdate><enddate>20140506</enddate><creator>NG CATHERINE BEE LIANG</creator><creator>DIMAANO ANTONIO JR B</creator><creator>ENG KIAN TENG</creator><creator>GAN RICHARD TE</creator><creator>WANG CHUEN KHIANG</creator><creator>SUTHIWONGSUNTHORN NATHAPONG</creator><creator>SAE LE KRIANGSAK</creator><scope>EVB</scope></search><sort><creationdate>20140506</creationdate><title>Semiconductor packages and methods of packaging semiconductor devices</title><author>NG CATHERINE BEE LIANG ; DIMAANO ANTONIO JR B ; ENG KIAN TENG ; GAN RICHARD TE ; WANG CHUEN KHIANG ; SUTHIWONGSUNTHORN NATHAPONG ; SAE LE KRIANGSAK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8716873B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NG CATHERINE BEE LIANG</creatorcontrib><creatorcontrib>DIMAANO ANTONIO JR B</creatorcontrib><creatorcontrib>ENG KIAN TENG</creatorcontrib><creatorcontrib>GAN RICHARD TE</creatorcontrib><creatorcontrib>WANG CHUEN KHIANG</creatorcontrib><creatorcontrib>SUTHIWONGSUNTHORN NATHAPONG</creatorcontrib><creatorcontrib>SAE LE KRIANGSAK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NG CATHERINE BEE LIANG</au><au>DIMAANO ANTONIO JR B</au><au>ENG KIAN TENG</au><au>GAN RICHARD TE</au><au>WANG CHUEN KHIANG</au><au>SUTHIWONGSUNTHORN NATHAPONG</au><au>SAE LE KRIANGSAK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor packages and methods of packaging semiconductor devices</title><date>2014-05-06</date><risdate>2014</risdate><abstract>A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Semiconductor packages and methods of packaging semiconductor devices |
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