Packing signed word elements from two source registers to saturated signed byte elements in destination register
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third pac...
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| creator | MENNEMEIER LARRY M MITTAL MILLIND YAARI YAAKOV PELEG ALEXANDER EITAN BENNY |
| description | An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8639914B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8639914B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8639914B23</originalsourceid><addsrcrecordid>eNqNy7EKwkAQhOE0FqK-w76AhUbEtBHFUlDrcF4mx2Gyd9xuCL69KYK2VgM_882zeDX25dmReMeoaQipJrTowCrUpNCRDoEk9MmCEpwXRRLSsRntk9ERTfb5VvysZ6oh6tmoD_yly2zWmFawmnaR0fl0P17WiKGCRGPB0OpxO-zzotjsym3-x-UDNB9D-Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packing signed word elements from two source registers to saturated signed byte elements in destination register</title><source>esp@cenet</source><creator>MENNEMEIER LARRY M ; MITTAL MILLIND ; YAARI YAAKOV ; PELEG ALEXANDER ; EITAN BENNY</creator><creatorcontrib>MENNEMEIER LARRY M ; MITTAL MILLIND ; YAARI YAAKOV ; PELEG ALEXANDER ; EITAN BENNY</creatorcontrib><description>An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140128&DB=EPODOC&CC=US&NR=8639914B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140128&DB=EPODOC&CC=US&NR=8639914B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MENNEMEIER LARRY M</creatorcontrib><creatorcontrib>MITTAL MILLIND</creatorcontrib><creatorcontrib>YAARI YAAKOV</creatorcontrib><creatorcontrib>PELEG ALEXANDER</creatorcontrib><creatorcontrib>EITAN BENNY</creatorcontrib><title>Packing signed word elements from two source registers to saturated signed byte elements in destination register</title><description>An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy7EKwkAQhOE0FqK-w76AhUbEtBHFUlDrcF4mx2Gyd9xuCL69KYK2VgM_882zeDX25dmReMeoaQipJrTowCrUpNCRDoEk9MmCEpwXRRLSsRntk9ERTfb5VvysZ6oh6tmoD_yly2zWmFawmnaR0fl0P17WiKGCRGPB0OpxO-zzotjsym3-x-UDNB9D-Q</recordid><startdate>20140128</startdate><enddate>20140128</enddate><creator>MENNEMEIER LARRY M</creator><creator>MITTAL MILLIND</creator><creator>YAARI YAAKOV</creator><creator>PELEG ALEXANDER</creator><creator>EITAN BENNY</creator><scope>EVB</scope></search><sort><creationdate>20140128</creationdate><title>Packing signed word elements from two source registers to saturated signed byte elements in destination register</title><author>MENNEMEIER LARRY M ; MITTAL MILLIND ; YAARI YAAKOV ; PELEG ALEXANDER ; EITAN BENNY</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8639914B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MENNEMEIER LARRY M</creatorcontrib><creatorcontrib>MITTAL MILLIND</creatorcontrib><creatorcontrib>YAARI YAAKOV</creatorcontrib><creatorcontrib>PELEG ALEXANDER</creatorcontrib><creatorcontrib>EITAN BENNY</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MENNEMEIER LARRY M</au><au>MITTAL MILLIND</au><au>YAARI YAAKOV</au><au>PELEG ALEXANDER</au><au>EITAN BENNY</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packing signed word elements from two source registers to saturated signed byte elements in destination register</title><date>2014-01-28</date><risdate>2014</risdate><abstract>An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Packing signed word elements from two source registers to saturated signed byte elements in destination register |
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