Micro-regions for auto place and route optimization
Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and...
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| creator | MYLIUS JOHN H RAJAGOPAL KARTHIK VATS SUPARN |
| description | Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8621412B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8621412B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8621412B13</originalsourceid><addsrcrecordid>eNrjZDD2zUwuytctSk3PzM8rVkjLL1JILC3JVyjISUxOVUjMS1Eoyi8tSVXILyjJzM2sSiwBKuNhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBUCdeakl8aHBFmZGhiaGRk6GxkQoAQCwbSxG</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Micro-regions for auto place and route optimization</title><source>esp@cenet</source><creator>MYLIUS JOHN H ; RAJAGOPAL KARTHIK ; VATS SUPARN</creator><creatorcontrib>MYLIUS JOHN H ; RAJAGOPAL KARTHIK ; VATS SUPARN</creatorcontrib><description>Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131231&DB=EPODOC&CC=US&NR=8621412B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131231&DB=EPODOC&CC=US&NR=8621412B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MYLIUS JOHN H</creatorcontrib><creatorcontrib>RAJAGOPAL KARTHIK</creatorcontrib><creatorcontrib>VATS SUPARN</creatorcontrib><title>Micro-regions for auto place and route optimization</title><description>Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD2zUwuytctSk3PzM8rVkjLL1JILC3JVyjISUxOVUjMS1Eoyi8tSVXILyjJzM2sSiwBKuNhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBUCdeakl8aHBFmZGhiaGRk6GxkQoAQCwbSxG</recordid><startdate>20131231</startdate><enddate>20131231</enddate><creator>MYLIUS JOHN H</creator><creator>RAJAGOPAL KARTHIK</creator><creator>VATS SUPARN</creator><scope>EVB</scope></search><sort><creationdate>20131231</creationdate><title>Micro-regions for auto place and route optimization</title><author>MYLIUS JOHN H ; RAJAGOPAL KARTHIK ; VATS SUPARN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8621412B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MYLIUS JOHN H</creatorcontrib><creatorcontrib>RAJAGOPAL KARTHIK</creatorcontrib><creatorcontrib>VATS SUPARN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MYLIUS JOHN H</au><au>RAJAGOPAL KARTHIK</au><au>VATS SUPARN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Micro-regions for auto place and route optimization</title><date>2013-12-31</date><risdate>2013</risdate><abstract>Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Micro-regions for auto place and route optimization |
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