Computer system including an interrupt controller

A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable...

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Hauptverfasser: YAMADA HIROMICHI, SHIMAMURA KOTARO, ISHIGURO YUICHI, KANEKAWA NOBUYASU
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creator YAMADA HIROMICHI
SHIMAMURA KOTARO
ISHIGURO YUICHI
KANEKAWA NOBUYASU
description A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8589612B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8589612B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8589612B23</originalsourceid><addsrcrecordid>eNrjZDB0zs8tKC1JLVIoriwuSc1VyMxLzilNycxLV0jMA3KAMkWlBSUKyfl5JUX5OTmpRTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JD402MLUwtLM0MjJyJgIJQCX-yxJ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Computer system including an interrupt controller</title><source>esp@cenet</source><creator>YAMADA HIROMICHI ; SHIMAMURA KOTARO ; ISHIGURO YUICHI ; KANEKAWA NOBUYASU</creator><creatorcontrib>YAMADA HIROMICHI ; SHIMAMURA KOTARO ; ISHIGURO YUICHI ; KANEKAWA NOBUYASU</creatorcontrib><description>A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20131119&amp;DB=EPODOC&amp;CC=US&amp;NR=8589612B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20131119&amp;DB=EPODOC&amp;CC=US&amp;NR=8589612B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMADA HIROMICHI</creatorcontrib><creatorcontrib>SHIMAMURA KOTARO</creatorcontrib><creatorcontrib>ISHIGURO YUICHI</creatorcontrib><creatorcontrib>KANEKAWA NOBUYASU</creatorcontrib><title>Computer system including an interrupt controller</title><description>A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB0zs8tKC1JLVIoriwuSc1VyMxLzilNycxLV0jMA3KAMkWlBSUKyfl5JUX5OTmpRTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JD402MLUwtLM0MjJyJgIJQCX-yxJ</recordid><startdate>20131119</startdate><enddate>20131119</enddate><creator>YAMADA HIROMICHI</creator><creator>SHIMAMURA KOTARO</creator><creator>ISHIGURO YUICHI</creator><creator>KANEKAWA NOBUYASU</creator><scope>EVB</scope></search><sort><creationdate>20131119</creationdate><title>Computer system including an interrupt controller</title><author>YAMADA HIROMICHI ; SHIMAMURA KOTARO ; ISHIGURO YUICHI ; KANEKAWA NOBUYASU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8589612B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMADA HIROMICHI</creatorcontrib><creatorcontrib>SHIMAMURA KOTARO</creatorcontrib><creatorcontrib>ISHIGURO YUICHI</creatorcontrib><creatorcontrib>KANEKAWA NOBUYASU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMADA HIROMICHI</au><au>SHIMAMURA KOTARO</au><au>ISHIGURO YUICHI</au><au>KANEKAWA NOBUYASU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Computer system including an interrupt controller</title><date>2013-11-19</date><risdate>2013</risdate><abstract>A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Computer system including an interrupt controller
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T15%3A34%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YAMADA%20HIROMICHI&rft.date=2013-11-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8589612B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true