Smart edge detector

Smart edge detector

This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHIEN JINN-YEH, YANG SHUUN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHIEN JINN-YEH
YANG SHUUN
description This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8575967B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8575967B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8575967B23</originalsourceid><addsrcrecordid>eNrjZBAOzk0sKlFITUlPVUhJLUlNLskv4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBFqbmppZm5k5GxkQoAQDcWiAg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Smart edge detector</title><source>esp@cenet</source><creator>CHIEN JINN-YEH ; YANG SHUUN</creator><creatorcontrib>CHIEN JINN-YEH ; YANG SHUUN</creatorcontrib><description>This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20131105&amp;DB=EPODOC&amp;CC=US&amp;NR=8575967B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,782,887,25571,76555</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20131105&amp;DB=EPODOC&amp;CC=US&amp;NR=8575967B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHIEN JINN-YEH</creatorcontrib><creatorcontrib>YANG SHUUN</creatorcontrib><title>Smart edge detector</title><description>This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAOzk0sKlFITUlPVUhJLUlNLskv4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBFqbmppZm5k5GxkQoAQDcWiAg</recordid><startdate>20131105</startdate><enddate>20131105</enddate><creator>CHIEN JINN-YEH</creator><creator>YANG SHUUN</creator><scope>EVB</scope></search><sort><creationdate>20131105</creationdate><title>Smart edge detector</title><author>CHIEN JINN-YEH ; YANG SHUUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8575967B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>CHIEN JINN-YEH</creatorcontrib><creatorcontrib>YANG SHUUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHIEN JINN-YEH</au><au>YANG SHUUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Smart edge detector</title><date>2013-11-05</date><risdate>2013</risdate><abstract>This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US8575967B2
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title Smart edge detector
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-04T21%3A59%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHIEN%20JINN-YEH&rft.date=2013-11-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8575967B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true