PCI express enhancements and extensions
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa...
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| creator | PARDO ILAN SHARMA DEBENDRA DAS MUTHRASANALLUR SRIDHAR BLANKENSHIP ROBERT BHATT AJAY AKIYAMA JAMES AJANOVIC JASMIN WAGH MAHESH FALIK OHAD RODGERS SCOTT DION HARRIMAN DAVID ROSENBLUTH MARK SHAMIA DORON VASUDEVAN ANIL TAMARI ERAN WEISSMANN ELIEZER BARRY PETER MENDELSON ABRAHAM SETHI PRASHANT |
| description | A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8549183B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8549183B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8549183B23</originalsourceid><addsrcrecordid>eNrjZFAPcPZUSK0oKEotLlZIzctIzEtOzU3NKylWSMxLAUqUpOYVZ-bnFfMwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUkvjQYAtTE0tDC2MnI2MilAAAU4Anzg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PCI express enhancements and extensions</title><source>esp@cenet</source><creator>PARDO ILAN ; SHARMA DEBENDRA DAS ; MUTHRASANALLUR SRIDHAR ; BLANKENSHIP ROBERT ; BHATT AJAY ; AKIYAMA JAMES ; AJANOVIC JASMIN ; WAGH MAHESH ; FALIK OHAD ; RODGERS SCOTT DION ; HARRIMAN DAVID ; ROSENBLUTH MARK ; SHAMIA DORON ; VASUDEVAN ANIL ; TAMARI ERAN ; WEISSMANN ELIEZER ; BARRY PETER ; MENDELSON ABRAHAM ; SETHI PRASHANT</creator><creatorcontrib>PARDO ILAN ; SHARMA DEBENDRA DAS ; MUTHRASANALLUR SRIDHAR ; BLANKENSHIP ROBERT ; BHATT AJAY ; AKIYAMA JAMES ; AJANOVIC JASMIN ; WAGH MAHESH ; FALIK OHAD ; RODGERS SCOTT DION ; HARRIMAN DAVID ; ROSENBLUTH MARK ; SHAMIA DORON ; VASUDEVAN ANIL ; TAMARI ERAN ; WEISSMANN ELIEZER ; BARRY PETER ; MENDELSON ABRAHAM ; SETHI PRASHANT</creatorcontrib><description>A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131001&DB=EPODOC&CC=US&NR=8549183B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131001&DB=EPODOC&CC=US&NR=8549183B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARDO ILAN</creatorcontrib><creatorcontrib>SHARMA DEBENDRA DAS</creatorcontrib><creatorcontrib>MUTHRASANALLUR SRIDHAR</creatorcontrib><creatorcontrib>BLANKENSHIP ROBERT</creatorcontrib><creatorcontrib>BHATT AJAY</creatorcontrib><creatorcontrib>AKIYAMA JAMES</creatorcontrib><creatorcontrib>AJANOVIC JASMIN</creatorcontrib><creatorcontrib>WAGH MAHESH</creatorcontrib><creatorcontrib>FALIK OHAD</creatorcontrib><creatorcontrib>RODGERS SCOTT DION</creatorcontrib><creatorcontrib>HARRIMAN DAVID</creatorcontrib><creatorcontrib>ROSENBLUTH MARK</creatorcontrib><creatorcontrib>SHAMIA DORON</creatorcontrib><creatorcontrib>VASUDEVAN ANIL</creatorcontrib><creatorcontrib>TAMARI ERAN</creatorcontrib><creatorcontrib>WEISSMANN ELIEZER</creatorcontrib><creatorcontrib>BARRY PETER</creatorcontrib><creatorcontrib>MENDELSON ABRAHAM</creatorcontrib><creatorcontrib>SETHI PRASHANT</creatorcontrib><title>PCI express enhancements and extensions</title><description>A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAPcPZUSK0oKEotLlZIzctIzEtOzU3NKylWSMxLAUqUpOYVZ-bnFfMwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUkvjQYAtTE0tDC2MnI2MilAAAU4Anzg</recordid><startdate>20131001</startdate><enddate>20131001</enddate><creator>PARDO ILAN</creator><creator>SHARMA DEBENDRA DAS</creator><creator>MUTHRASANALLUR SRIDHAR</creator><creator>BLANKENSHIP ROBERT</creator><creator>BHATT AJAY</creator><creator>AKIYAMA JAMES</creator><creator>AJANOVIC JASMIN</creator><creator>WAGH MAHESH</creator><creator>FALIK OHAD</creator><creator>RODGERS SCOTT DION</creator><creator>HARRIMAN DAVID</creator><creator>ROSENBLUTH MARK</creator><creator>SHAMIA DORON</creator><creator>VASUDEVAN ANIL</creator><creator>TAMARI ERAN</creator><creator>WEISSMANN ELIEZER</creator><creator>BARRY PETER</creator><creator>MENDELSON ABRAHAM</creator><creator>SETHI PRASHANT</creator><scope>EVB</scope></search><sort><creationdate>20131001</creationdate><title>PCI express enhancements and extensions</title><author>PARDO ILAN ; SHARMA DEBENDRA DAS ; MUTHRASANALLUR SRIDHAR ; BLANKENSHIP ROBERT ; BHATT AJAY ; AKIYAMA JAMES ; AJANOVIC JASMIN ; WAGH MAHESH ; FALIK OHAD ; RODGERS SCOTT DION ; HARRIMAN DAVID ; ROSENBLUTH MARK ; SHAMIA DORON ; VASUDEVAN ANIL ; TAMARI ERAN ; WEISSMANN ELIEZER ; BARRY PETER ; MENDELSON ABRAHAM ; SETHI PRASHANT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8549183B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>PARDO ILAN</creatorcontrib><creatorcontrib>SHARMA DEBENDRA DAS</creatorcontrib><creatorcontrib>MUTHRASANALLUR SRIDHAR</creatorcontrib><creatorcontrib>BLANKENSHIP ROBERT</creatorcontrib><creatorcontrib>BHATT AJAY</creatorcontrib><creatorcontrib>AKIYAMA JAMES</creatorcontrib><creatorcontrib>AJANOVIC JASMIN</creatorcontrib><creatorcontrib>WAGH MAHESH</creatorcontrib><creatorcontrib>FALIK OHAD</creatorcontrib><creatorcontrib>RODGERS SCOTT DION</creatorcontrib><creatorcontrib>HARRIMAN DAVID</creatorcontrib><creatorcontrib>ROSENBLUTH MARK</creatorcontrib><creatorcontrib>SHAMIA DORON</creatorcontrib><creatorcontrib>VASUDEVAN ANIL</creatorcontrib><creatorcontrib>TAMARI ERAN</creatorcontrib><creatorcontrib>WEISSMANN ELIEZER</creatorcontrib><creatorcontrib>BARRY PETER</creatorcontrib><creatorcontrib>MENDELSON ABRAHAM</creatorcontrib><creatorcontrib>SETHI PRASHANT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARDO ILAN</au><au>SHARMA DEBENDRA DAS</au><au>MUTHRASANALLUR SRIDHAR</au><au>BLANKENSHIP ROBERT</au><au>BHATT AJAY</au><au>AKIYAMA JAMES</au><au>AJANOVIC JASMIN</au><au>WAGH MAHESH</au><au>FALIK OHAD</au><au>RODGERS SCOTT DION</au><au>HARRIMAN DAVID</au><au>ROSENBLUTH MARK</au><au>SHAMIA DORON</au><au>VASUDEVAN ANIL</au><au>TAMARI ERAN</au><au>WEISSMANN ELIEZER</au><au>BARRY PETER</au><au>MENDELSON ABRAHAM</au><au>SETHI PRASHANT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PCI express enhancements and extensions</title><date>2013-10-01</date><risdate>2013</risdate><abstract>A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | PCI express enhancements and extensions |
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