Digital hold in a phase-locked loop

A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL a...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	YU QICHENG, SEETHAMRAJU SRISAI R, HEIN JERRELL P, WONG KENNETH KIN WAI
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS
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