Semiconductor device, semiconductor device testing method, and data processing system

To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal...

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Hauptverfasser: EGUCHI TAKANORI, YOKO HIDEYUKI, IDE AKIRA, SHIBATA KAYOKO, SHIGEZANE YASUYUKI, TANAMACHI KENICHI, OGAWA NAOKI, HIDAKA KAZUO
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creator EGUCHI TAKANORI
YOKO HIDEYUKI
IDE AKIRA
SHIBATA KAYOKO
SHIGEZANE YASUYUKI
TANAMACHI KENICHI
OGAWA NAOKI
HIDAKA KAZUO
description To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8498831B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8498831B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8498831B23</originalsourceid><addsrcrecordid>eNqNirEKAjEQBdNYiPoP-wFnoWcRW0WxP68-luSpAZMNt6vg34tgaWE1MDNT13fIKUiJj2AyUsQzBTSkPywZ1FK5UobdJDbEJVJkY6qjBKh-mr7UkOducuG7YvHlzNHxcN6flqgyQCsHFNjQd36z9b5d7dbtH8sbs3s5hA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device, semiconductor device testing method, and data processing system</title><source>esp@cenet</source><creator>EGUCHI TAKANORI ; YOKO HIDEYUKI ; IDE AKIRA ; SHIBATA KAYOKO ; SHIGEZANE YASUYUKI ; TANAMACHI KENICHI ; OGAWA NAOKI ; HIDAKA KAZUO</creator><creatorcontrib>EGUCHI TAKANORI ; YOKO HIDEYUKI ; IDE AKIRA ; SHIBATA KAYOKO ; SHIGEZANE YASUYUKI ; TANAMACHI KENICHI ; OGAWA NAOKI ; HIDAKA KAZUO</creatorcontrib><description>To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130730&amp;DB=EPODOC&amp;CC=US&amp;NR=8498831B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130730&amp;DB=EPODOC&amp;CC=US&amp;NR=8498831B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>EGUCHI TAKANORI</creatorcontrib><creatorcontrib>YOKO HIDEYUKI</creatorcontrib><creatorcontrib>IDE AKIRA</creatorcontrib><creatorcontrib>SHIBATA KAYOKO</creatorcontrib><creatorcontrib>SHIGEZANE YASUYUKI</creatorcontrib><creatorcontrib>TANAMACHI KENICHI</creatorcontrib><creatorcontrib>OGAWA NAOKI</creatorcontrib><creatorcontrib>HIDAKA KAZUO</creatorcontrib><title>Semiconductor device, semiconductor device testing method, and data processing system</title><description>To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirEKAjEQBdNYiPoP-wFnoWcRW0WxP68-luSpAZMNt6vg34tgaWE1MDNT13fIKUiJj2AyUsQzBTSkPywZ1FK5UobdJDbEJVJkY6qjBKh-mr7UkOducuG7YvHlzNHxcN6flqgyQCsHFNjQd36z9b5d7dbtH8sbs3s5hA</recordid><startdate>20130730</startdate><enddate>20130730</enddate><creator>EGUCHI TAKANORI</creator><creator>YOKO HIDEYUKI</creator><creator>IDE AKIRA</creator><creator>SHIBATA KAYOKO</creator><creator>SHIGEZANE YASUYUKI</creator><creator>TANAMACHI KENICHI</creator><creator>OGAWA NAOKI</creator><creator>HIDAKA KAZUO</creator><scope>EVB</scope></search><sort><creationdate>20130730</creationdate><title>Semiconductor device, semiconductor device testing method, and data processing system</title><author>EGUCHI TAKANORI ; YOKO HIDEYUKI ; IDE AKIRA ; SHIBATA KAYOKO ; SHIGEZANE YASUYUKI ; TANAMACHI KENICHI ; OGAWA NAOKI ; HIDAKA KAZUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8498831B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>EGUCHI TAKANORI</creatorcontrib><creatorcontrib>YOKO HIDEYUKI</creatorcontrib><creatorcontrib>IDE AKIRA</creatorcontrib><creatorcontrib>SHIBATA KAYOKO</creatorcontrib><creatorcontrib>SHIGEZANE YASUYUKI</creatorcontrib><creatorcontrib>TANAMACHI KENICHI</creatorcontrib><creatorcontrib>OGAWA NAOKI</creatorcontrib><creatorcontrib>HIDAKA KAZUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>EGUCHI TAKANORI</au><au>YOKO HIDEYUKI</au><au>IDE AKIRA</au><au>SHIBATA KAYOKO</au><au>SHIGEZANE YASUYUKI</au><au>TANAMACHI KENICHI</au><au>OGAWA NAOKI</au><au>HIDAKA KAZUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device, semiconductor device testing method, and data processing system</title><date>2013-07-30</date><risdate>2013</risdate><abstract>To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title Semiconductor device, semiconductor device testing method, and data processing system
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T00%3A02%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=EGUCHI%20TAKANORI&rft.date=2013-07-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8498831B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true