Method of fabricating a device using low temperature anneal processes, a device and design structure

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method inclu...

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Hauptverfasser: NARASIMHA SHREESH, KANE TERENCE L, ONTALUS VIOREL, WANG YUN-YU, DOMENICUCCI ANTHONY G, NUMMY KAREN A
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creator NARASIMHA SHREESH
KANE TERENCE L
ONTALUS VIOREL
WANG YUN-YU
DOMENICUCCI ANTHONY G
NUMMY KAREN A
description A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title Method of fabricating a device using low temperature anneal processes, a device and design structure
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