Non-volatile semiconductor memory storing an inverse map for rebuilding a translation table

A non-volatile semiconductor memory comprising (1) a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address and (2) a volatile memory. Upon a power-up of the non-volatile semiconductor memory, a translation table is generated in the volatile memory for mapping logical addresses to physical addresses in the non-volatile memory array. The generating includes reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array. The logical address corresponds to a physical address of one of the memory segments. In response to determining that the memory segment corresponding to the logical address is valid, the translation table is updated using the logical address.