Resistor and manufacturing method thereof

A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region,...

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Hauptverfasser: LIN CHUN-HSIEN, HSU SHIHIEH, WANG YAOANG, PAI CHI-HORN, YANG JIE-NING, TSENG CHI-SHENG
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creator LIN CHUN-HSIEN
HSU SHIHIEH
WANG YAOANG
PAI CHI-HORN
YANG JIE-NING
TSENG CHI-SHENG
description A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8477006B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8477006B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8477006B23</originalsourceid><addsrcrecordid>eNrjZNAMSi3OLC7JL1JIzEtRyE3MK01LTC4pLcrMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRYm5uYGBmZORsZEKAEA3VAo0g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Resistor and manufacturing method thereof</title><source>esp@cenet</source><creator>LIN CHUN-HSIEN ; HSU SHIHIEH ; WANG YAOANG ; PAI CHI-HORN ; YANG JIE-NING ; TSENG CHI-SHENG</creator><creatorcontrib>LIN CHUN-HSIEN ; HSU SHIHIEH ; WANG YAOANG ; PAI CHI-HORN ; YANG JIE-NING ; TSENG CHI-SHENG</creatorcontrib><description>A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRICITY ; RESISTORS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130702&amp;DB=EPODOC&amp;CC=US&amp;NR=8477006B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130702&amp;DB=EPODOC&amp;CC=US&amp;NR=8477006B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN CHUN-HSIEN</creatorcontrib><creatorcontrib>HSU SHIHIEH</creatorcontrib><creatorcontrib>WANG YAOANG</creatorcontrib><creatorcontrib>PAI CHI-HORN</creatorcontrib><creatorcontrib>YANG JIE-NING</creatorcontrib><creatorcontrib>TSENG CHI-SHENG</creatorcontrib><title>Resistor and manufacturing method thereof</title><description>A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRICITY</subject><subject>RESISTORS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAMSi3OLC7JL1JIzEtRyE3MK01LTC4pLcrMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRYm5uYGBmZORsZEKAEA3VAo0g</recordid><startdate>20130702</startdate><enddate>20130702</enddate><creator>LIN CHUN-HSIEN</creator><creator>HSU SHIHIEH</creator><creator>WANG YAOANG</creator><creator>PAI CHI-HORN</creator><creator>YANG JIE-NING</creator><creator>TSENG CHI-SHENG</creator><scope>EVB</scope></search><sort><creationdate>20130702</creationdate><title>Resistor and manufacturing method thereof</title><author>LIN CHUN-HSIEN ; HSU SHIHIEH ; WANG YAOANG ; PAI CHI-HORN ; YANG JIE-NING ; TSENG CHI-SHENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8477006B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRICITY</topic><topic>RESISTORS</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN CHUN-HSIEN</creatorcontrib><creatorcontrib>HSU SHIHIEH</creatorcontrib><creatorcontrib>WANG YAOANG</creatorcontrib><creatorcontrib>PAI CHI-HORN</creatorcontrib><creatorcontrib>YANG JIE-NING</creatorcontrib><creatorcontrib>TSENG CHI-SHENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN CHUN-HSIEN</au><au>HSU SHIHIEH</au><au>WANG YAOANG</au><au>PAI CHI-HORN</au><au>YANG JIE-NING</au><au>TSENG CHI-SHENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Resistor and manufacturing method thereof</title><date>2013-07-02</date><risdate>2013</risdate><abstract>A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRICITY
RESISTORS
title Resistor and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T13%3A50%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIN%20CHUN-HSIEN&rft.date=2013-07-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8477006B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true