Thin film transistor array panel and method for manufacturing the same

Thin film transistor array panel and method for manufacturing the same

A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and c...

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Hauptverfasser: JEONG YU-GWANG, YANG DONG-JU, LEE KI-YEUP, SONG JEAN-HO, CHOI SHIN-IL
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator JEONG YU-GWANG
YANG DONG-JU
LEE KI-YEUP
SONG JEAN-HO
CHOI SHIN-IL
description A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8450737B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8450737B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8450737B23</originalsourceid><addsrcrecordid>eNqNyjEOwjAMQNEsDAi4gy-AhCiozEVU7JS5slqHREqcyHYHbg8DB2D6w_tr1w8hMviYMpgga1QrAiiCb6jIlAB5hkwWygz-Sxl58TjZIpFfYIFAMdPWrTwmpd2vGwf9bbje91TLSFpxIiYbn4_L6Xxom7Y7Nn8sH82LM1w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Thin film transistor array panel and method for manufacturing the same</title><source>esp@cenet</source><creator>JEONG YU-GWANG ; YANG DONG-JU ; LEE KI-YEUP ; SONG JEAN-HO ; CHOI SHIN-IL</creator><creatorcontrib>JEONG YU-GWANG ; YANG DONG-JU ; LEE KI-YEUP ; SONG JEAN-HO ; CHOI SHIN-IL</creatorcontrib><description>A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130528&amp;DB=EPODOC&amp;CC=US&amp;NR=8450737B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130528&amp;DB=EPODOC&amp;CC=US&amp;NR=8450737B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JEONG YU-GWANG</creatorcontrib><creatorcontrib>YANG DONG-JU</creatorcontrib><creatorcontrib>LEE KI-YEUP</creatorcontrib><creatorcontrib>SONG JEAN-HO</creatorcontrib><creatorcontrib>CHOI SHIN-IL</creatorcontrib><title>Thin film transistor array panel and method for manufacturing the same</title><description>A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEOwjAMQNEsDAi4gy-AhCiozEVU7JS5slqHREqcyHYHbg8DB2D6w_tr1w8hMviYMpgga1QrAiiCb6jIlAB5hkwWygz-Sxl58TjZIpFfYIFAMdPWrTwmpd2vGwf9bbje91TLSFpxIiYbn4_L6Xxom7Y7Nn8sH82LM1w</recordid><startdate>20130528</startdate><enddate>20130528</enddate><creator>JEONG YU-GWANG</creator><creator>YANG DONG-JU</creator><creator>LEE KI-YEUP</creator><creator>SONG JEAN-HO</creator><creator>CHOI SHIN-IL</creator><scope>EVB</scope></search><sort><creationdate>20130528</creationdate><title>Thin film transistor array panel and method for manufacturing the same</title><author>JEONG YU-GWANG ; YANG DONG-JU ; LEE KI-YEUP ; SONG JEAN-HO ; CHOI SHIN-IL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8450737B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JEONG YU-GWANG</creatorcontrib><creatorcontrib>YANG DONG-JU</creatorcontrib><creatorcontrib>LEE KI-YEUP</creatorcontrib><creatorcontrib>SONG JEAN-HO</creatorcontrib><creatorcontrib>CHOI SHIN-IL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEONG YU-GWANG</au><au>YANG DONG-JU</au><au>LEE KI-YEUP</au><au>SONG JEAN-HO</au><au>CHOI SHIN-IL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Thin film transistor array panel and method for manufacturing the same</title><date>2013-05-28</date><risdate>2013</risdate><abstract>A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Thin film transistor array panel and method for manufacturing the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T05%3A02%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JEONG%20YU-GWANG&rft.date=2013-05-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8450737B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true