DC/DC converter having a fast and accurate average current limit

Three modifications are provided to obtain a fast and accurate average current limit in a DC/DC converter. The first modification relates to providing a bias signal control configured to apply a variable DC bias signal to the compensation ramp signal generated in the DC/DC converter so that the compensating ramp signal is biased to zero at the end of each ON-time for each cycle so that the peak current limit is independent of the duty cycle of the pulse width modulation signal during current limit conditions. A second modification relates to modulating the clamp voltage that establishes the peak current limit as a function of ripple of the inductor current for each cycle of the pulse width modulation signal so as to reduce or cancel the effect of the inductor ripple current on the average output current during current limit conditions. The third modification relates to adjusting the frequency of the pulse width modulation signal during current limit conditions as a function of both the input voltage and the output voltage of the DC/DC converter.