Input circuit and semiconductor storage device
According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a...
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| creator | SHIMIZU YUUI |
| description | According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8410811B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8410811B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8410811B23</originalsourceid><addsrcrecordid>eNrjZNDzzCsoLVFIzixKLs0sUUjMS1EoTs3NTM7PSylNLskvUigGEonpqQopqWWZyak8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-NNjCxNDAwtDQyciYCCUAybIqjw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Input circuit and semiconductor storage device</title><source>esp@cenet</source><creator>SHIMIZU YUUI</creator><creatorcontrib>SHIMIZU YUUI</creatorcontrib><description>According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130402&DB=EPODOC&CC=US&NR=8410811B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130402&DB=EPODOC&CC=US&NR=8410811B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIMIZU YUUI</creatorcontrib><title>Input circuit and semiconductor storage device</title><description>According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzzCsoLVFIzixKLs0sUUjMS1EoTs3NTM7PSylNLskvUigGEonpqQopqWWZyak8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-NNjCxNDAwtDQyciYCCUAybIqjw</recordid><startdate>20130402</startdate><enddate>20130402</enddate><creator>SHIMIZU YUUI</creator><scope>EVB</scope></search><sort><creationdate>20130402</creationdate><title>Input circuit and semiconductor storage device</title><author>SHIMIZU YUUI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8410811B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIMIZU YUUI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIMIZU YUUI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Input circuit and semiconductor storage device</title><date>2013-04-02</date><risdate>2013</risdate><abstract>According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
| title | Input circuit and semiconductor storage device |
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