Logic design verification techniques for liveness checking with retiming

A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liv...

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Bibliographische Detailangaben

Hauptverfasser:	WILLIAMS MARK ALLEN, BOBOK GABOR, BAUMGARTNER JASON R, ROESSLER PAUL JOSEPH
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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