Reverse ALD
A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the fi...
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| creator | ADETUTU OLUBUNMI O TRIYOSO DINA H |
| description | A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl. |
| format | Patent |
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Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CHEMICAL SURFACE TREATMENT ; CHEMISTRY ; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL ; COATING MATERIAL WITH METALLIC MATERIAL ; COATING METALLIC MATERIAL ; DECORATIVE ARTS ; DIFFUSION TREATMENT OF METALLIC MATERIAL ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL ; METALLURGY ; MOSAICS ; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25 ; NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE ; PAPERHANGING ; PERFORMING OPERATIONS ; PRODUCING DECORATIVE EFFECTS ; SEMICONDUCTOR DEVICES ; TARSIA WORK ; TRANSPORTING</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130326&DB=EPODOC&CC=US&NR=8404594B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130326&DB=EPODOC&CC=US&NR=8404594B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ADETUTU OLUBUNMI O</creatorcontrib><creatorcontrib>TRIYOSO DINA H</creatorcontrib><title>Reverse ALD</title><description>A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CHEMICAL SURFACE TREATMENT</subject><subject>CHEMISTRY</subject><subject>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</subject><subject>COATING MATERIAL WITH METALLIC MATERIAL</subject><subject>COATING METALLIC MATERIAL</subject><subject>DECORATIVE ARTS</subject><subject>DIFFUSION TREATMENT OF METALLIC MATERIAL</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL</subject><subject>METALLURGY</subject><subject>MOSAICS</subject><subject>MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25</subject><subject>NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE</subject><subject>PAPERHANGING</subject><subject>PERFORMING OPERATIONS</subject><subject>PRODUCING DECORATIVE EFFECTS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TARSIA WORK</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOAOSi1LLSpOVXD0ceFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRYmBiamliZORsZEKAEAgy4clQ</recordid><startdate>20130326</startdate><enddate>20130326</enddate><creator>ADETUTU OLUBUNMI O</creator><creator>TRIYOSO DINA H</creator><scope>EVB</scope></search><sort><creationdate>20130326</creationdate><title>Reverse ALD</title><author>ADETUTU OLUBUNMI O ; TRIYOSO DINA H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8404594B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CHEMICAL SURFACE TREATMENT</topic><topic>CHEMISTRY</topic><topic>COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL</topic><topic>COATING MATERIAL WITH METALLIC MATERIAL</topic><topic>COATING METALLIC MATERIAL</topic><topic>DECORATIVE ARTS</topic><topic>DIFFUSION TREATMENT OF METALLIC MATERIAL</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL</topic><topic>METALLURGY</topic><topic>MOSAICS</topic><topic>MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25</topic><topic>NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE</topic><topic>PAPERHANGING</topic><topic>PERFORMING OPERATIONS</topic><topic>PRODUCING DECORATIVE EFFECTS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TARSIA WORK</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>ADETUTU OLUBUNMI O</creatorcontrib><creatorcontrib>TRIYOSO DINA H</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ADETUTU OLUBUNMI O</au><au>TRIYOSO DINA H</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Reverse ALD</title><date>2013-03-26</date><risdate>2013</risdate><abstract>A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DECORATIVE ARTS DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY MOSAICS MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25 NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE PAPERHANGING PERFORMING OPERATIONS PRODUCING DECORATIVE EFFECTS SEMICONDUCTOR DEVICES TARSIA WORK TRANSPORTING |
| title | Reverse ALD |
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