Increased DRAM-array throughput using inactive bitlines

A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel...

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Bibliographische Detailangaben

Hauptverfasser:	HARVARD QAWI I, DROST ROBERT J, BAKER R. JACOB
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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