Resolving global coupling timing and slew violations for buffer-dominated designs

A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determ...

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Bibliographische Detailangaben

Hauptverfasser:	MAHMUD TUHIN, LI ZHUO, ALPERT CHARLES J, CLABES JOACHIM G, QUAY STEPHEN T
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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